Apparatus for designing semiconductor integrated circuit, method of designing semiconductor integrated circuit, and program for designing semiconductor integrated circuit

ABSTRACT

A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section.

TECHNICAL FIELD

The present invention relates to technologies for semiconductorintegrated circuit design.

BACKGROUND ART

Synchronous semiconductor integrated circuits are generally realized insuch a manner that a flip-flop circuit in a circuit is synchronized to aclock. In the synchronous semiconductor integrated circuits, the maximumvalue of a delay in propagation time between flip-flop circuits in acircuit determines the frequency of the clock to which the flip-flopcircuits are synchronized. It is not true that a shorter delay inpropagation between flip-flop circuits is always preferable. That is,because of a period of time after which the flip-flop circuit will beable to read data, or a time difference of a clock supplied to twoflip-flop circuits connected by a propagating signal, a delay inpropagation of a certain time (a period of time equal to or longer thana certain time) is required to be defined between individual flip-flopcircuits. For example, without such a delay of a certain time betweenflip-flop circuits connected by a propagating signal, a previous clocksignal is picked up by the flip-flop circuit as data. This results in afailure. Such a failure is referred to as a hold error. Techniques forpreventing the hold error have been proposed (PTLs 1-8, and NPL 1).

A system for designing a semiconductor integrated circuit in NPL 1comprises semiconductor integrated circuit data, a circuit delaymeasurement system, a delay buffer insertion deciding system, and adelay buffer inserting system. In this system, the circuit delaymeasurement system first measures a delay in a pair of flip-flopcircuits between which a signal propagates. Next, the delay bufferinsertion deciding system decides where a hold error is likely to occurusing a result of the measurement. The delay buffer inserting systemthen inserts a delay buffer for generating a delay to prevent occurrenceof a hold error. For example, in a case that two flip-flop circuits aredirectly connected with each other without any circuit element forgenerating a delay and a hold error is expected to occur, a delay gateis inserted by this system for designing a semiconductor integratedcircuit. This eliminates a hold error (see FIG. 9).

A system for designing a semiconductor integrated circuit as disclosedin PTL 1 comprises semiconductor integrated circuit data, a circuitdelay measurement system, a latch circuit insertion deciding system, anda latch circuit inserting system. In this system, the circuit delaymeasurement system first measures a delay in a pair of flip-flopcircuits between which a signal propagates. Next, the latch circuitinsertion deciding system decides where a hold error is likely to occurusing a result of the measurement. Then, the latch circuit insertingsystem inserts a latch circuit that blocks signal transmission in a halfof a clock cycle and permits signal transmission in the other half of aclock cycle. As a result, a delay equivalent to a half of a clock cycleis given to a signal line with a hold error. For example, in a case thattwo flip-flop circuits are directly connected with each other withoutany circuit element for generating a delay and a hold error is expectedto occur, a latch circuit is inserted by this semiconductor integratedcircuit design system. Thus, a delay equivalent to a half of a clockcycle is inserted. This eliminates a hold error (see FIGS. 9, 10).

In PTL 2, a design technique using a latch circuit is proposed. However,the technique is extremely difficult to adapt to a design techniqueapplied to common flip-flop-based synchronization circuits.

According to PTL 3, there is a description as “If a flip-flop circuitunder any of these conditions can be divided into latch circuits, thedivision is determined according to conditions such as a delay time in apreceding path and a delay in a subsequent path.” There is also adescription as “the clock cycle period is set longer by a predeterminedvalue and the logic circuits are arranged, and the flip-flop circuitsrelated to an error path on which an error for the target clock cycleoccurs are replaced by latch circuits to rearrange the logic circuits inthe pipeline design using flip-flop circuits. It is, therefore, possibleto increase the permissible maximum logic delay time of a logic path andto easily design a pipeline.”

According to PTL 4, there is a description as “a signal line connectingsystem in accordance with this embodiment is comprised of: a logicdesign data memory section for storing therein logic design data for asemiconductor device; a program storage section for storing thereinprograms or the like for analyzing timing of signal lines to create anew via connection pattern; a position/connection information memorysection for storing therein information about the position andconnection of logic elements; a timing information memory section forstoring therein timing analysis information for a signal delay inpropagation time in a signal line; a via information memory section forstoring therein via information for a signal line formed in a differentredistribution layer and connected through a via; a processing controlsection comprising means for executing a series of signal lineconnecting processing; an output device for outputting a result of theprocessing via an input/output control section; and an input device forinputting a command and the like to the processing control section.”There is also a description as “There are provided signal lineconnecting method and system in which a signal delay in propagation timesufficient for controlling timing between logic elements is given.”

According to PTL 5, there is a description as “for hierarchical design,comprising: a plurality of timing distribution production sectionsindividually provided corresponding to a plurality of designhierarchical layers, and each of which receives block informationregarding a function of a circuit from a respective timing informationdatabase having netlist information regarding a wiring line scheme andoutputs a respective timing distribution value obtained by distributinga delay value produced by a delay element of the circuit; and aninter-hierarchical layer association manager for dynamically changingconnections between said plurality of timing distribution productionsections and transmitting and receiving modification informationregarding the respective timing distribution value to and from saidplurality of timing distribution production sections.” There is also adescription as “when the timing specifications are changed, a range ofthe influence of the change can be referred to immediately, andconsequently, a reference mistake upon such change of the specificationsis eliminated. Further, the combination of provisional wiring and actualwiring can achieve both of augmentation of an execution speed of floorplanning and augmentation of an accuracy. Furthermore, a hierarchicalentity can be used and a distributed design environment can beconstructed. Further, in top-down design, only a necessary portion canbe particularized, and it can be examined whether timing specificationsdivided by trial and examination are appropriate or not by one designteam. Consequently, problems upon implementing can be estimated andotherwise possible iterations can be reduced.”

According to PTL 6, there is a description as “In the delay optimizationunit, there is the step of inserting a level latch circuit in a signalpath violating said minimum delay constraints, wherein the step ofinserting comprises the steps of: calculating the frequency of overlapof each output terminal included in said synchronous sequential circuitwith signal paths violating the minimum delay constraints; and insertingsaid level latch circuit in a signal path in the descending order ofsaid frequency of overlap such that an LSI layout pattern area of saidsynchronous sequential circuit is minimized.” There is also adescription as “the calculation processing time can be reduced becausethe maximum delay time is not affected. Moreover, the increase in theLSI layout pattern area in the synchronous sequential circuit can bereduced.”

According to PTL 7, there are a description as “a method for designing asemiconductor integrated circuit using pattern data for a flip flopfunction device including a flip flop forming means for receiving aclock signal and a data signal, a latch forming means for receiving theclock signal and an output signal of the flip flop forming means, afirst output terminal for outputting a signal from the flip flop formingmeans, and a second output terminal for outputting a signal from thelatch forming means, the method characterized in including the steps ofdesigning a circuit by forming a data path with the first outputterminal; inspecting hold time in a latter stage device of the datapath; and connecting the latter stage device to the second outputterminal instead of the first output terminal when found in theinspection that there is a possibility of occurrence of a hold timeviolation,” and a description as “an apparatus for designing asemiconductor integrated circuit using pattern data for a flip flopfunction device including a flip flop forming means for receiving aclock signal and a data signal, a latch forming means for receiving theclock signal and an output signal of the flip flop forming means, afirst output terminal for outputting a signal from the flip flop formingmeans, a second output terminal for outputting a signal from the latchforming means, the apparatus characterized in including: a designprocessing means for designing a circuit by forming a data path with thefirst output terminal; a hold time inspecting means for inspecting holdtime in a latter stage device of the data path; and a data pathcorrecting means for connecting the latter stage device to the secondoutput terminal instead of the first output terminal when found in theinspection that there is a possibility of occurrence of a hold timeviolation.”

According to PTL 8, an object is “to provide a method of designinglayout of a semiconductor integrated circuit in which, in a case thatthere is no space in a hold error path for disposing a buffer foreliminating a hold error or in a case that there is space for disposingthe buffer but a setup error is introduced, a point for inserting abuffer preventing a new delay error can be searched for by moving othercells, duplicating a line or modifying line connection, thereby avoidingrepetition of ECO layout”, and there is a description as “a method ofdesigning layout of a semiconductor integrated circuit, the methodcharacterized in comprising the steps of performing initialpositioning/connection by initial positioning/connecting means based ona netlist for a semiconductor integrated circuit to create layoutinformation; performing extraction of line resistance and line capacity,delay calculation, and static timing analysis by RC extraction/delaycalculation/static timing analysis means based on said layoutinformation to create line resistance/line capacity information and holderror path/slack information; making a decision about thepresence/absence of a hold error by hold error presence/absence decidingmeans based on said hold error path/slack information, and in a casethat a hold error is present, creating information on a penalty requiredto search for a point for inserting a buffer for eliminating a holderror by penalty information creating means based on said layoutinformation and said hold error path/slack information; and performingsearch for and determination of said insertion point and delaycoordination by buffer insertion point searching/determining/delaycoordinating means based on said penalty information.” However, nodescription of a flip-flop circuit is found in PTL 8.

CITATION LIST Patent Literature

-   PTL 1: JP-P2677256B-   PTL 2: JP-P2005-277909A-   PTL 3: JP-P2003-234643A-   PTL 4: JP-P2005-26390A-   PTL 5: JP-P2007-188517A-   PTL 6: JP-P1997-008143A-   PTL 7: JP-P2007-142094A-   PTL 8: JP-P2008-217642A

Non Patent Literature

-   NPL 1: “Circuits, Interconnections, and Packaging for VLSI,” edited    and translated by Kisaburou NAKAZAWA and Hiroshi NAKAMURA, published    by MARUZEN Co., Ltd., pp. 356-358

SUMMARY OF INVENTION Technical Problem

PTLs 1-8 and NPL 1 above do not propose concrete techniques for solvingthe following two problems.

The first problem is that a design technique for eliminating a holderror by inserting a delay gate in a semiconductor integrated circuitexperiencing a hold error causes a significant increase of the area. Adelay gate for intentionally generating a delay is fabricated bystacking common gate circuit elements in order to intentionally generatea delay. This requires a large area. It is expected that this trend willbe accelerated in the super submicron process in the future. Even at acurrent process level, the circuit area is roughly doubled to eliminatea hold error. Especially for two directly connected flip-flops, toeliminate a hold error having a comparatively great value, it isnecessary to generate a large number of delays (that is, to insert agate requiring a large area). When transistors are sped up by asubmicron process in the future, a delay gate having a still larger areamust be inserted.

Techniques involving inserting a latch in a semiconductor integratedcircuit (see PTLs above) may often eliminate a hold error between twoflip-flops. However, the techniques involving inserting a latch giverise to a second problem. Specifically, in a case that a clock suppliedto the inserted latch circuit is not properly timed per se, a delayvalue cannot be inserted at a proper time. It is also difficult tocontrol clock timing for the inserted latch.

Accordingly, a problem to be solved by the present invention is toprovide a design apparatus (design system) for a semiconductorintegrated circuit that causes a reduced increase of the area requiredto eliminate a hold error and can be easily controlled for a signalpropagating between flip-flop circuits in a case that a comparativelygreat delay value should be inserted or in a case that an error (setuperror) due to too great a delay value should be prevented afterinserting a comparatively great delay.

Solution to Problem

The aforementioned problem is solved by:

an apparatus for designing a semiconductor integrated circuit includingflip-flop circuits, said apparatus characterized in comprising:

a timing analyzing section for detecting a hold error according totiming analysis data including values at input and output nodes of saidflip-flop circuits, and identifying a node experiencing said hold error;

a fall FF/buffer insertion determining section for determining insertionof a fall FF or a buffer in said hold error position based on a resultof the analysis by said timing analyzing section;

a fall FF inserting section for inserting a fall FF in said hold errorposition located to insert a fall FF based on fall FF insertion positiondata from said fall FF/buffer insertion determining section, andconnecting a clock line to said inserted fall FF; and

a buffer inserting section for inserting a buffer in said hold errorposition located to insert a buffer based on buffer insertion positiondata from said fall FF/buffer insertion determining section.

The aforementioned problem is solved by:

a method of designing a semiconductor integrated circuit includingflip-flop circuits in which a hold error is remedied, said methodcharacterized in comprising:

an analyzing step at which a timing analyzing section detects a holderror based on semiconductor integrated circuit design data andidentifies a node experiencing said hold error;

a fall FF/buffer insertion determining step at which a fall FF/bufferinsertion determining section determines insertion of a fall FF or abuffer in said hold error position based on a result of the analysis bysaid timing analyzing step;

a fall FF inserting step at which a fall FF inserting section inserts afall FF in said hold error position located to insert a fall FF based onfall FF insertion position data from said fall FP/buffer insertiondetermining step, and connects a clock line to said inserted fall FF;and

a buffer inserting step at which a buffer inserting section inserts abuffer in said hold error position located to insert a buffer based onbuffer insertion position data from said fall FF/buffer insertiondetermining step.

The aforementioned problem is solved by:

a program causing a computer to design a semiconductor integratedcircuit including flip-flop circuits, said program characterized incausing said computer to function as:

a timing analyzing section for detecting a hold error according totiming analysis data including values at input and output nodes of saidflip-flop circuits, and identifying a node experiencing said hold error;

a fall FF/buffer insertion determining section for determining insertionof a fall FF or a buffer in said hold error position based on a resultof the analysis by said timing analyzing section;

a fall FF inserting section for inserting a fall. FF in said hold errorposition located to insert a fall FF based on fall FF insertion positiondata from said fall FF/buffer insertion determining section, andconnecting a clock line to said inserted fall FF; and

a buffer inserting section for inserting a buffer in said hold errorposition located to insert a buffer based on buffer insertion positiondata from said fall FF/buffer insertion determining section.

Advantageous Effects of Invention

For a signal propagating between flip-flop circuits, a hold error thatoccurs in a signal line having a delay value smaller than anindividually set delay value is eliminated. An increase of the arearequired for the elimination of a hold error is small. In inserting agreat delay, the arrival time of a clock signal at the inserted elementcan be easily controlled.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 A schematic diagram of a semiconductor integrated circuit designapparatus of one embodiment in accordance with the present invention.

FIG. 2 A schematic diagram of the semiconductor integrated circuitdesign apparatus in FIG. 1 implemented by a computer.

FIG. 3 A flow chart of a semiconductor integrated circuit design methodof one embodiment in accordance with the present invention.

FIG. 4 A flow chart for a fall FF inserting section.

FIG. 5 A flow chart for a buffer inserting section.

FIG. 6 An explanatory diagram representing an example of fall FFinsertion.

FIG. 7 A timing chart for fall FF insertion.

FIG. 8 An explanatory diagram representing an example of bufferinsertion.

FIG. 9 An explanatory diagram for conventional remedies against a holderror.

FIG. 10 A timing chart for conventional remedies against a hold error(as by inserting a latch).

DESCRIPTION OF EMBODIMENTS

An apparatus for designing a semiconductor integrated circuit inaccordance with the present invention is an apparatus for designing asemiconductor integrated circuit including flip-flop circuits. Theaforementioned apparatus has a timing analyzing section. Theaforementioned timing analyzing section detects a hold error accordingto timing analysis data including values at input and output nodes ofthe aforementioned flip-flop circuits, and identifies a nodeexperiencing the aforementioned hold error. The aforementioned timinganalyzing section preferably detects a hold error according to timinganalysis data including values at input and output nodes of theaforementioned flip-flop circuits and the arrival time of a clocksupplied to the aforementioned flip-flops, and identities a node betweenflip-flops experiencing the aforementioned hold error. Theaforementioned timing analyzing section preferably detects a hold errorbased on semiconductor integrated circuit design data, and identifies anode experiencing the aforementioned hold error. The aforementionedapparatus has a fall FF/buffer insertion determining section. Theaforementioned fall FF/buffer insertion determining section determinesinsertion of a fall FF or a buffer in the hold error position based on aresult of the analysis by the aforementioned timing analyzing section.The aforementioned fall FF/buffer insertion determining sectionpreferably determines which of a fall FF or a buffer to insert based onwhether all hold error positions cause a setup error after inserting adelay equivalent to a half of a clock cycle. The aforementionedapparatus has a fall FF inserting section. The aforementioned fall FFinserting section inserts a fall FF at the aforementioned hold errorposition located to insert a fall FF based on fall FF insertion positiondata from the aforementioned fall FF/buffer insertion determiningsection, and connects a clock line to the inserted fall FF. Theaforementioned fall FF inserting section preferably inserts a fall FF inthe aforementioned hold error position based on the aforementionedsemiconductor integrated circuit design data and the fall FF insertionposition data from the aforementioned fall FF/buffer insertiondetermining section, and connects a clock line to the inserted fall FF.The aforementioned apparatus has a buffer inserting section. Theaforementioned buffer inserting section inserts a buffer in theaforementioned hold error position located to insert a buffer based onbuffer insertion position data from the aforementioned fall FF/bufferinsertion determining section. The aforementioned buffer insertingsection preferably inserts a buffer in the aforementioned hold errorposition based on the aforementioned semiconductor integrated circuitdesign data and the buffer insertion position data from theaforementioned fall FF/buffer insertion determining section. Theaforementioned apparatus preferably further has a database in which thesemiconductor integrated circuit design data is stored.

A method of designing a semiconductor integrated circuit in accordancewith the present invention is a method of designing a semiconductorintegrated circuit including flip-flop circuits in which a hold error isremedied. The aforementioned method has an analysis step. Theaforementioned analysis step is a step by a timing analyzing section fordetecting a hold error based on semiconductor integrated circuit designdata and identifying a node experiencing the aforementioned hold error.The aforementioned analysis step is preferably a step by a timinganalyzing section for detecting a hold error according to timinganalysis data including values at input and output nodes of theaforementioned flip-flop circuits and the arrival time of a clocksupplied to the flip-flops, and identifying a node between flip-flopsexperiencing the aforementioned hold error. The aforementioned methodhas a fall FF/buffer insertion determining step. The aforementioned fallFF/buffer insertion determining step is a step by a fall FF/bufferinsertion determining section for determining insertion of a fall FF ora buffer in the aforementioned hold error position based on a result ofthe analysis by the aforementioned analyzing step. The aforementionedmethod has a fall FF insertion step. The aforementioned fall FFinsertion step is a step by a fall FF inserting section for inserting afall FF in the aforementioned hold error position located to insert afall FF based on fall FF insertion position data from the aforementionedfall FF/buffer insertion determining step, and connecting a clock lineto the inserted fall FF. The aforementioned method has a bufferinsertion step. The aforementioned buffer insertion step is a step by abuffer inserting section for inserting a buffer in the aforementionedhold error position located to insert a buffer based on buffer insertionposition data from the aforementioned fall FF/buffer insertiondetermining step. The aforementioned method is preferably a methodperformed by the apparatus for designing a semiconductor integratedcircuit of the aforementioned present invention.

A program for designing a semiconductor integrated circuit in accordancewith the present invention is a program causing a computer to design asemiconductor integrated circuit including flip-flop circuits. Thisprogram is a program causing the computer to function as theaforementioned timing analyzing section, the aforementioned fallFF/buffer insertion determining section, the aforementioned fall FFinserting section, and the aforementioned buffer inserting section.Alternatively, it is a program causing the computer to perform theaforementioned method. The program is written into a storage medium.

The present invention effects a significant advantage in eliminating ahold error. For example, an increase of the area required for theelimination of a hold error is small. In inserting a great delay, thearrival time of a clock signal at the inserted element can be easilycontrolled.

For example, as compared with the delay gate insertion method or latchcircuit insertion method that merely inserts a circuit element, thepresent invention in which a fall flip-flop is inserted can achieve acomparatively great delay, such as a half of a clock cycle, with asmaller area, such as a single flip-flop. Especially in a case that adelay gate is employed to control a timing inconsistency problem causedby line connection with increasing capacity by miniaturization in thefuture and caused by circuit elements with an improved operation speedby miniaturization, several tens of buffers are required in inserting adelay of the order of a half of a clock cycle. In view of the fact, thetechnique of the present invention can address the problem with a verysmall area. Because of such a small area, power consumption can bereduced.

The present invention inserts a flip-flop for latching fall data.Therefore, it is unnecessary to adjust a lag in the arrival time of aclock at the inserted element itself. Specifically, a fall of the clockoccurs in a half of a clock cycle. Thus, even in a case that the arrivaltime of the clock fall is somewhat shifted, a delay of a half of a cycleof the clock can be accurately given to a position for insertion. Ascompared with a theoretically ideal condition without any shift,collapse due to a shift caused by latch insertion is prevented unless apremature arrival time of the clock by a time greater than a half of aclock cycle is encountered.

Since a flip-flop for latching fall data is inserted, it is unnecessaryto take account of testing for extracting non-defective parts regardingthe fall flip-flop to be inserted. For example, the fall flip-flop isused only for the purpose of inserting a delay. Thus, it is unnecessaryto perform a test with a value supplied from the external by a scan.

Now the present invention will be described in more detail.

It should be noted that the present invention is not limited to theembodiment below, and it may be modified as appropriate within a scopeof the technical concept of the present invention.

First Embodiment

FIG. 1 is a schematic diagram of a semiconductor integrated circuitdesign apparatus of one embodiment in accordance with the presentinvention.

An apparatus for designing a semiconductor integrated circuit (a designaid system for a semiconductor integrated circuit) of this embodimenthas a function block 102, a function block 104, a function block 106,and a function block 107. It also has databases (memories) 101, 103, 105and 108 associated with the function blocks 102, 104, 106 and 107.

The function block 102 is a timing analyzing section. The function block104 is a fall FF/buffer insertion determining section. The functionblock 106 is a fall FF inserting section. The function block 107 is abuffer inserting section.

The database 101 is a semiconductor integrated circuit design database.Data stored in the database 101 are those to be output to the timinganalyzing section 102, the fall FF inserting section 106, and the bufferinserting section 107. The database 103 is a timing analysis database.Data stored in the database 103 are those output by the timing analyzingsection 102. Data stored in the database 103 are those to be output tothe fall FF/buffer insertion determining section 104. The database 105is a fall FF/buffer insertion position database. Data stored in thedatabase 105 are those output by the fall FF/buffer insertiondetermining section 104. Data stored in the database 105 are those to beoutput to the fall FF inserting section 106 (or the buffer insertingsection 107). The database 108 is a hold-error-remedied semiconductorintegrated circuit design database. Data stored in the database 108 is aresult output from the function blocks 106 and 107. The data is alsohold-error-remedied semiconductor integrated circuit design data.

In general, these function blocks each operate as follows:

The timing analyzing section 102 determines a delay in propagation incircuit elements in a semiconductor integrated circuit and a delay inpropagation between flip-flop circuits. Particularly, the followingtiming analysis technique is employed: A delay between adjacent circuitelement gates and a delay in a line are each calculated. The calculatedvalues are used to analyze a delay value between the circuit elementgates, a delay value for propagation in a connection between connectedflip-flop circuits, and a difference in arrival time of a clock at theflip-flops. Then, a delay position and a delay value in the circuitarrangement are identified on a gate or circuit block level, and areoutput as timing analysis data. The timing analysis data are stored inthe timing analysis database (memory) 103. The timing analysistechniques that can be employed include element-level simulation,delayed gate level simulation, and post layout simulation. Inparticular, Primetime (trademark), TimeMill (trademark), or SPICE(trademark) available from Synopsys (U.S.) are employed.

The fall FF/buffer insertion determining section 104 determines a linebetween two flip-flops in which a fall FF can be inserted based on thedata from the timing analysis database 103. Specifically, all holderrors are detected from the timing analysis database 103. For such ahold error, a decision is made as to whether a setup error occurs afterinserting a delay of the order of a half of a clock cycle. In a casethat a setup error does not occur, it is decided to insert a fall FF. Ina case that a setup error occurs, it is decided to insert a buffer. Thefall FF/buffer insertion determining section 104 outputs the decision tothe fall FF/buffer insertion position database 105. This decision isabout which of a fall FF or a buffer to insert for each hold error.

The fall FF inserting section 106 inserts a fall FF at a position of thehold error at which it is decided to insert a fall FF based on the datafrom the semiconductor integrated circuit design database 101 and thedata from the fall FF/buffer insertion position database 105. Theprocessing is simplified when the position for insertion is determinedas a point before a flip-flop on the output side. However, insertion maybe made at any position. Insertion may be made at any position on theoutput side. The same clock signal as that for the flip-flops on bothends is connected to a clock input of the flip-flop. The result isoutput to the hold-error-remedied semiconductor integrated circuitdesign database 108.

The buffer inserting section 107 inserts a buffer at a position of thehold error at which it is decided to insert a buffer based on the datafrom the semiconductor integrated circuit design database 101 and thedata from the fall FF/buffer insertion position database 105. Theprocessing is simplified when the position for insertion is determinedas a point before a flip-flop on the output side. However, insertion maybe made at any position. For example, insertion may be made at anyposition on the output side. This inserted buffer is a buffer with whicha hold error can be eliminated (or a number of buffers required toeliminate a hold error). The result is output to the hold-error-remediedsemiconductor integrated circuit design database 108.

Each database is generally constructed as follows:

The semiconductor integrated circuit design database 101 stores thereina gate-level netlist for designing/manufacturing a semiconductorintegrated circuit, an HDL, and library data including delay data andprocess data. It also stores therein a single chip or core level data.Further, it also stores therein simulatable data (such as, for example,delay information taking account of line connection including the linelength and line capacity etc. extracted from layout data). That is, datarequired in designing/manufacturing a semiconductor integrated circuitare stored.

The timing analysis database 103 stores therein resulting data fromtiming analysis by the timing analyzing section 102. For example, inputsignals for testing and electric potential displacement informationalong a time axis of each node are stored.

The fall FF/buffer insertion position database 105 stores therein dataof all hold errors. It also stores therein data as to which of a fall FFor a buffer to insert for a hold error. Such data are those determinedby the fall FF/buffer insertion determining section 104.

The hold-error-remedied semiconductor integrated circuit design database108 stores therein data for semiconductor integrated circuit design. Thedata is hold-error-remedied semiconductor integrated circuit design databy the fall FF inserting section 106 (or the buffer inserting section107).

A block diagram of the present invention configured in a centralprocessing unit (computer) is shown in FIG. 2.

The apparatus for designing a semiconductor integrated circuit (thedesign aid system for a semiconductor integrated circuit) of the presentinvention has a central processing unit (CPU) 3, a program memory 5, anda database memory 7. The program memory 5 stores therein the timinganalyzing section 102, the fall FF/buffer insertion determining section104, the fall FF inserting section 106, and the buffer inserting section107. These function blocks 102, 104, 106 and 107 may be stored in theprogram memory 5 and may be run in cooperation with the centralprocessing unit 3, or they may be transferred to another memory deviceto be run. The database memory 7 stores therein the semiconductorintegrated circuit design database 101, the timing analysis database103, the fall FF/buffer insertion position database 105, and thehold-error-remedied semiconductor integrated circuit design database108. Memories for use as the program memory 5 and the database memory 7may be any one of magnetic memories, semiconductor memories or memoriesby other techniques.

The central processing unit (CPU) 3 runs the computer program (software)loaded from the program memory 5. This causes the apparatus fordesigning a semiconductor integrated circuit in FIG. 2 to achievefunctions of the function blocks in FIG. 1.

Next, an operation of the apparatus for designing a semiconductorintegrated circuit in FIGS. 1 and 2 will be described (see FIGS. 3-8).

First, the timing analyzing section 102 makes a request for datanecessary to the semiconductor integrated circuit design database 101.The semiconductor integrated circuit design database 101 stores thereindesign data for use in designing a semiconductor integrated circuit(before manufacturing the semiconductor integrated circuit). Based onthe data obtained from the semiconductor integrated circuit designdatabase 101, the timing analyzing section 102 uses an appropriate testpattern to calculate a delay in propagation between logic element gatesand a delay in propagation between flip-flop circuits as timing analysisdata (S1).

The timing analyzing section 102 decides the presence/absence ofoccurrence of a hold error from the calculated delays in propagationbetween logic element gates and between flip-flop circuits (S2 (see FIG.3)).

In a case that no hold error occurs, the timing analyzing section 102terminates the timing analysis (S3).

In a case that a hold error occurs, the fall FF/buffer insertiondetermining section 104 uses a result of the timing analysis in whichdelay-in-propagation information is stored in the timing analysisdatabase 103, to measure timing for each hold error occurring positionafter inserting a delay equivalent to a half of a clock cycle in thehold error position. Then, a decision is made as to whether a setuperror occurs (S4, S5, S6).

In a case that no setup error occurs, a fall FF is inserted in the holderror position (S7). Then, the presence/absence of a hold error ischecked (S2). Depending upon the presence/absence of the error, theprocess goes to Step S3 or S4 described above.

In a case that a setup error occurs, a buffer is inserted in the holderror position (S8). Then, the presence/absence of a hold error ischecked (S2). Depending upon the presence/absence of the error, theprocess goes to Step S3 or S4 described above.

As remedies against each hold error stored in the fall FF/bufferinsertion position database 105, the fall FF inserting section 106inserts a fall FF in a line experiencing a hold error for which a fallFF is to be inserted, and supplies the same clock as that for theflip-flops on both ends (see FIG. 4).

As remedies against each hold error stored in the fall FF/bufferinsertion position database 105, the buffer inserting section 107inserts a buffer in a line experiencing a hold error for which a bufferfor eliminating the hold error is to be inserted (see FIG. 5).

As a result, a hold error having a great value is eliminated.

FIG. 9 shows an exemplary hold error and a conventional remedialtechnique for amending the hold error. Too small a signal propagationvalue between the flip-flops, in which the arrival times of the clock atthe flip-flops on both sides are taken into account, causes a holderror. For this problem, there are known methods of blocking a signalover a half of a cycle using the techniques as proposed in theaforementioned prior art literature, “buffer insertion” and “latchinsertion.”

The “buffer insertion” technique in the prior art literature, however,requires a large number of buffers to be inserted for a hold error witha comparatively great value due to enhancement in speed ofsemiconductors. The “latch insertion” technique in the prior artliterature requires a clock to be rigorously supplied to a latch to beinserted (see FIG. 10). For a clock waveform shown in FIG. 10, dataslips off. As a result, remedies against a hold error cannot be applied.

Thus, a fall FF is inserted between two FFs and the same clock as thatfor the FFs on both ends is supplied to the fall FF to be inserted (seeFIG. 6). This gives leading and trailing margins of a half of a clockcycle with respect to the clock supplied to the fall FF. Therefore, evenwhen some offset is present between the arrival time of the clock at theFFs on both ends and that at the fall FF to be inserted, a delayequivalent to a half of a clock cycle can be inserted for an offset ofthe order of a half of a clock cycle (see FIG. 7).

It should be noted that in inserting a fall FF, a delay equivalent to ahalf of a clock cycle is inserted. Thus, there is a risk of a delayequal to or greater than the clock cycle generated between theflip-flops. In such a case, a buffer is inserted as needed (see FIG. 8).

The technique in the embodiment described above eliminates a failurefactor in designing a semiconductor integrated circuit caused by toosmall a delay in propagation in which the arrival times of the clock attwo the flip-flop circuits are taken into account, referred to as holderror. Yet, an increase of the area required is small. Moreover, thetechnique is simple.

The preceding description addresses an example in which the presenttechnique is applied to a synchronous circuit by FF circuits in which aCLK (clock) signal is input to both FFs to serve as a set signal in theset/reset flip-flop circuit. However, it will be easily recognized thatthe present technique may be applied to an asynchronous circuit operatedby recognizing input data by other circuits than CLK as a set signal.Moreover, when the phrase “position in the circuit arrangement” is usedin this specification, it refers to a position in a schematic circuitarrangement and a physical position in layout.

Part or all of the aforementioned embodiment may be described as in thefollowing Appendixes; however, the present invention is not limitedthereto.

(Appendix 1) An apparatus for designing a semiconductor integratedcircuit including flip-flop circuits, said apparatus comprising:

a timing analyzing section for detecting a hold error according totiming analysis data including values at input and output nodes of saidflip-flop circuits, and identifying a node experiencing said hold error;

a fall FF/buffer insertion determining section for determining insertionof a fall FF or a buffer in said hold error position based on a resultof the analysis by said timing analyzing section;

a fall FF inserting section for inserting a fall FF in said hold errorposition located to insert a fall FF based on fall FF insertion positiondata from said fall FF/buffer insertion determining section, andconnecting a clock line to said inserted fall FF; and

a buffer inserting section for inserting a buffer in said hold errorposition located to insert a buffer based on buffer insertion positiondata from said fall FF/buffer insertion determining section.

(Appendix 2) The semiconductor integrated circuit design apparatus asrecited in Appendix 1, wherein said apparatus further comprises adatabase in which semiconductor integrated circuit design data isstored,

said timing analyzing section is a section for detecting a hold errorbased on said semiconductor integrated circuit design data, andidentifying a node experiencing said hold error,

said fall FF inserting section is a section for inserting a fall FF insaid hold error position based on said semiconductor integrated circuitdesign data and fall FF insertion position data from said fall FF/bufferinsertion determining section, and connecting a clock line to saidinserted fall FF, and

said buffer inserting section is a section for inserting a buffer insaid hold error position based on said semiconductor integrated circuitdesign data and buffer insertion position data from said fall FF/bufferinsertion determining section.

(Appendix 3) The semiconductor integrated circuit design apparatus asrecited in Appendix 1 or 2, wherein said fall FF/buffer insertiondetermining section is a section for determining which of a fall FF or abuffer to insert based on whether all hold error positions experience asetup error after inserting a delay equivalent to a half of a clockcycle.

(Appendix 4) A method of designing a semiconductor integrated circuitincluding flip-flop circuits in which a hold error is remedied,comprising:

an analyzing step at which a timing analyzing section detects a holderror based on semiconductor integrated circuit design data andidentifies a node experiencing said hold error;

a fall FF/buffer insertion determining step at which a fall FF/bufferinsertion determining section determines insertion of a fall FF or abuffer in said hold error position based on a result of the analysis bysaid timing analyzing step;

a fall FF inserting step at which a fall FF inserting section inserts afall FF in said hold error position located to insert a fall FF based onfall FF insertion position data from said fall FF/buffer insertiondetermining step, and connects a clock line to said inserted fall FF;and

a buffer inserting step at which a buffer inserting section inserts abuffer in said hold error position located to insert a buffer based onbuffer insertion position data from said fall FF/buffer insertiondetermining step.

(Appendix 5) A program causing a computer to design a semiconductorintegrated circuit including flip-flop circuits, said program causingsaid computer to function as:

a timing analyzing section for detecting a hold error according totiming analysis data including values at input and output nodes of saidflip-flop circuits, and identifying a node experiencing said hold error;

a fall FF/buffer insertion determining section for determining insertionof a fall FF or a buffer in said hold error position based on a resultof the analysis by said timing analyzing section;

a fall FF inserting section for inserting a fall FF in said hold errorposition located to insert a fall FF based on fall FF insertion positiondata from said fall FF/buffer insertion determining section, andconnecting a clock line to said inserted fall FF; and

a buffer inserting section for inserting a buffer in said hold errorposition located to insert a buffer based on buffer insertion positiondata from said fall FF/buffer insertion determining section.

The present application claims priority based on Japanese PatentApplication No. 2009-49916 filed on Mar. 3, 2009, the disclosure ofwhich is incorporated herein in its entirety.

REFERENCE SIGNS LIST

-   -   3 Central processing unit (CPU)    -   5 Program memory    -   102 Timing analyzing section    -   104 Fall FF/buffer insertion determining section    -   106 Fall FF inserting section    -   107 Buffer inserting section    -   7 Database memory    -   101 Semiconductor integrated circuit design database    -   103 Timing analysis database    -   105 Fall FF/buffer insertion position database    -   108 Hold-error-remedied semiconductor integrated circuit design        database

1. An apparatus for designing a semiconductor integrated circuitincluding flip-flop circuits, comprising: a timing analyzing sectionthat detects a hold error according to timing analysis data includingvalues at input and output nodes of said flip-flop circuits, andidentifies a node experiencing said hold error; a fall FF/bufferinsertion determining section that determines insertion of a fall FF ora buffer in said hold error position based on a result of the analysisby said timing analyzing section; a fall FF inserting section thatinserts a fall FF in said hold error position located to insert a fallFF based on fall FF insertion position data from said fall FF/bufferinsertion determining section, and connects a clock line to saidinserted fall FF; and a buffer inserting section that inserts a bufferin said hold error position located to insert a buffer based on bufferinsertion position data from said fall FF/buffer insertion determiningsection.
 2. An apparatus for designing a semiconductor integratedcircuit according to claim 1, wherein said apparatus further comprises adatabase in which semiconductor integrated circuit design data isstored, said timing analyzing section is a section that detects a holderror based on said semiconductor integrated circuit design data, andidentifies a node experiencing said hold error, said fall FF insertingsection is a section that inserts a fall FF in said hold error positionbased on said semiconductor integrated circuit design data and fall FFinsertion position data from said fall FF/buffer insertion determiningsection, and connects a clock line to said inserted fall FF, and saidbuffer inserting section is a section that inserts a buffer in said holderror position based on said semiconductor integrated circuit designdata and buffer insertion position data from said fall FF/bufferinsertion determining section.
 3. An apparatus for designing asemiconductor integrated circuit according to claim 1, wherein said fallFF/buffer insertion determining section is a section that determineswhich of a fall FF or a buffer to insert based on whether all hold errorpositions experience a setup error after inserting a delay equivalent toa half of a clock cycle.
 4. A method of designing a semiconductorintegrated circuit including flip-flop circuits in which a hold error isremedied, comprising: an analyzing step at which a timing analyzingsection detects a hold error based on semiconductor integrated circuitdesign data and identifies a node experiencing said hold error; a fallFF/buffer insertion determining step at which a fall FF/buffer insertiondetermining section determines insertion of a fall FF or a buffer insaid hold error position based on a result of the analysis by saidanalyzing step; a fall FF inserting step at which a fall FF insertingsection inserts a fall FF in said hold error position located to inserta fall FF based on fall FF insertion position data from said fallFF/buffer insertion determining step, and connects a clock line to saidinserted fall FF; and a buffer inserting step at which a bufferinserting section inserts a buffer in said hold error position locatedto insert a buffer based on buffer insertion position data from saidfall FF/buffer insertion determining step.
 5. A non-transitorycomputer-readable storage medium storing a program causing a computer todesign a semiconductor integrated circuit including flip-flop circuits,said program causing said computer to function as: a timing analyzingsection that detects a hold error according to timing analysis dataincluding values at input and output nodes of said flip-flop circuits,and identifies a node experiencing said hold error; a fall FF/bufferinsertion determining section that determines insertion of a fall FF ora buffer in said hold error position based on a result of the analysisby said timing analyzing section; a fall FF inserting section thatinserts a fall FF in said hold error position located to insert a fallFF based on fall FF insertion position data from said fall FF/bufferinsertion determining section, and connects a clock line to saidinserted fall FF; and a buffer inserting section that inserts a bufferin said hold error position located to insert a buffer based on bufferinsertion position data from said fall FF/buffer insertion determiningsection.